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CESC 222-Digital Circuit Design

CESC 222-Digital Circuit Design

8.2 Simulation Problem

he problems contained in the following Design and Simulation document are Mealy sequential circuit design and simulation problems. These problems are of approximately equal difficulty, and different students are assigned different problems by the instructor. You are asked to use the following procedure:

  1. Derive a state graph and state table for the assigned problem. Reduce the table to a minimum number of states. Check the reduced table using the LogicAid state table checker. Encoded solution files are found in the Lab 16 folder.
  2. Make a state assignment using the guidelines. Derive the transition table, and then derive the D flip-flop input equations and output equation(s) using Karnaugh maps.
  3. Use LogicAid to derive the same equations and verify that the equations derived in step (2) are correct. Then derive one or more sets of equations for different state assignments using LogicAid.
  4. Design the circuit using NAND gates, NOR gates, and three D flip-flops. Choose the equations from step (3) that lead to the lowest cost circuit, and make sure that it meets the specifications.
  5. Input the logic circuit into SimUaid using switches for the X input, clock, reset, and preset inputs. Use probes for the Z output and flip-flop outputs. Use SimUaid to verify the transition table by presetting the flip-flops to each state and observing the next state outputs. Then use SimUaid to manually test the operation of the circuit by applying the required test sequences and observing the outputs, being very careful to read the outputs at the proper time.
  6. Replace the clock and X input switches with a clock module and an input device. Program the input device to produce the proper test waveform. Display the simulator timing waveforms for clock, X, Z, and the flip-flop outputs. Print the waveforms and mark the times to read the Z output. Verify that the output sequence is correct.
  7. Replace the X and reset switches and the Z probe with a checker module (found on the SimUaid device menu), run the checker and verify that the circuit passes the test. The checker automatically generates input sequences and verifies that the output sequences are correct. Test files to use with the checker are provided in the SimUaid/Checkers directory on the CD that came with the textbook.

After verifying your design is correct and meets the specifications, you will implement your design in hardware using the following steps:

  • Use SimUaid to generate a VHDL file from your circuit file.
  • Use the Vivado software to synthesize the circuit from the VHDL file.
  • Generate a programming file and download it to the FPGA on the Basys 3 hardware board.
  • Test your circuit manually using the switches on the hardware board for the clock, reset, and X inputs. Use the same test sequence as you did in step (5).

Submit the complete SimUaid circuit, the VHDL code generated by SimUaid, and the logic equations for the flip-flop inputs and for Z.

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